The inventive concepts described herein relate to a memory system, and more particularly, to an interface device which interfaces information between a semiconductor memory device and a memory controller.
The need for low-power and high-density memories are increasing to improve the performance of electronic systems.
For implementation of the low-power and high-density memories, a high bandwidth memory is receiving attention to provide high performance in situations such as low-power high-speed operation.
An LPDDR (Low Power Double Data Rate) type of Dynamic Random Access Memory (DRAM) mounted in a mobile device is a semiconductor memory device that operates at a low-power double data rate. The semiconductor memory device can be controlled by a memory controller communicating with a processor or System on Chip (SoC). In read operation mode, the memory controller receives read data using a data strobe signal.
When a ground termination type of on-die termination operation is performed in a differential receiver of an interface device and a data strobe signal is not provided from a semiconductor memory device, a dirty signal of tri-state condition may be outputted from the differential receiver.